r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 978

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
Rev. 1.00 Oct. 01, 2007 Page 912 of 1956
REJ09B0256-0100
Bit
25
24
23
22
21
Bit Name
RABT
RFCOF

ECI
TC[0]
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R
R
R/W
Description
Receive Abort Detect
Indicates that the E-MAC aborts receiving a frame
because of failures during frame reception.
0: Frame reception has not been aborted or no
1: Frame reception has been aborted
Receive Frame Counter Overflow
Indicates that the frame counter in the receive FIFO
has overflowed.
0: Receive frame counter has not overflowed
1: Receive frame counter has overflowed
Reserved
This bit is always read as 0. The write value should
always be 0.
E-MAC Status Register Source
This bit is a read-only bit. When the source of an ECSR
interrupt is cleared, this bit is also cleared.
0: E-MAC status interrupt source has not been detected
1: E-MAC status interrupt source has been detected
Frame Transmission Complete
Indicates, in combination with the TC[1] bit, that all the
data specified by the transmit descriptor has been
transmitted from the E-MAC. For details, see the
description of the TC[1] bit.
reception directive