r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 342

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 9 Interrupt Controller (INTC)
9.3.18
INT2MSKR is a 32-bit readable/writable register that sets masking for each source indicated in
the interrupt source register. Interrupts whose corresponding bits in INT2MSKRG are set to 1 are
not notified to the CPU.
INT2MSKR is initialized to H'FFFF FFFF (mask state) by a reset.
Initial value:
Initial value:
Rev. 1.00 Oct. 01, 2007 Page 276 of 1956
REJ09B0256-0100
Bit
31 to 26 —
25
24
23
22
21
20
19
18
17
16
15
14
R/W:
R/W:
Bit:
Bit:
Interrupt Mask Register (INT2MSKR)
Bit Name
GPIO
—
SSI0
MMCIF
—
SIOF0
PCIC5
PCIC4
PCIC3
PCIC2
PCIC1
PCIC0
PCIC1 PCIC0 HAC CMT
R/W
31
15
−
R
1
1
R/W
30
−
14
R
1
1
Initial
Value
All 1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
29
13
−
R
1
1
R/W
28
12
−
R
1
1
27
11
−
−
R
R
R/W
R
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
26
10
−
−
R
R
1
1
Function
These bits are always read as 1.
The write value should always be
1.
Masks GPIO interrupts
This bit is always read as 1. The
write value should always be 1.
Masks SSI0 interrupts
Masks MMCIF interrupts
This bit is always read as 1. The
write value should always be 1.
Masks SIOF0 interrupts
Masks PCIC5 interrupts
Masks PCIC4 interrupts
Masks PCIC3 interrupts
Masks PCIC2 interrupts
Masks PCIC1 interrupts
Masks PCIC0 interrupts
GPIO
R/W
25
−
R
1
9
1
DMAC H-UDI
R/W
24
−
R
1
8
1
SSI0 MMCIF
R/W
R/W
23
1
7
1
R/W
22
−
R
1
6
1
WDT
R/W
21
−
R
1
5
1
SIOF0 PCIC5 PCIC4 PCIC3 PCIC2
SCIF1 SCIF0
R/W
R/W
20
1
4
1
R/W
R/W
Description
Masks interrupts
for each peripheral
module.
[When writing]
0: Invalid
1: Interrupts are
[When reading]
0: No mask setting
1: Mask setting
19
1
3
1
masked
R/W
RTC TMU1 TMU0
R/W
18
1
2
1
R/W
R/W
17
1
1
1
R/W
R/W
16
1
0
1