r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 295

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

8.3
8.3.1
L memory access from the CPU and FPU is direct via the instruction bus and operand bus by
means of the virtual address. As long as there is no conflict on the page, the L memory is accessed
in one cycle.
8.3.2
L memory is always accessed by the SuperHyway bus master module, such as DMAC, via the
SuperHyway bus which is a physical address bus. The same addresses as for the virtual addresses
must be used.
8.3.3
High-speed data transfer can be performed through block transfer between the L memory and
external memory without cache utilization.
Data can be transferred from the external memory to the L memory through a prefetch instruction
(PREF). Block transfer from the external memory to the L memory begins when the PREF
instruction is issued to the address in the L memory area in the virtual address space.
Data can be transferred from the L memory to the external memory through a write-back
instruction (OCBWB). Block transfer from the L memory to the external memory begins when the
OCBWB instruction is issued to the address in the L memory area in the virtual address space.
In either case, transfer rate is fixed to 32 bytes. Since the start address is always limited to a 32-
byte boundary, the lower five bits of the address indicated by Rn are ignored, and are always dealt
with as all 0s. In either case, other pages and cache can be accessed during block transfer, but the
CPU will stall if the page which is being transferred is accessed before data transfer ends.
The physical addresses [28:0] of the external memory performing data transfers with the L
memory are specified as follows according to whether the MMU is enabled or disabled.
(1)
An address of the L memory area is specified to the UTLB VPN field, and to the physical address
of the transfer source (in the case of the PREF instruction) or the transfer destination (in the case
When MMU is Enabled (MMUCR.AT = 1) and RAMCR.RP = 1
Operation
Access from the CPU and FPU
Access from the SuperHyway Bus Master Module
Block Transfer
Rev. 1.00 Oct. 01, 2007 Page 229 of 1956
Section 8 L Memory
REJ09B0256-0100