r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 415

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Bit
11
10 to 8
7
6 to 4
Bit Name

WTH

BSH
Initial
Value
0
111
0
000
R/W
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
WEn Hold Cycle (WEn Negate–CSn Negate Delay
Cycle)
Specify the number of cycles to be inserted to ensure
the WEn hold time to the T2. However, setting to over 1
cycle for insertion, one cycle incremented for the setting
value when address hold cycle is set to over 1 cycle.
(Available only when the SRAM interface, byte control
SRAM interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
BS Hold Cycle
Specify the number of cycles to be inserted to elongate
the BS assertion time. (Available only when the SRAM
interface, byte control SRAM interface, or burst ROM
interface is selected.)
000: 1 cycle inserted
001: 2 cycles inserted
010: Setting prohibited
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Section 11 Local Bus State Controller (LBSC)
Rev. 1.00 Oct. 01, 2007 Page 349 of 1956
REJ09B0256-0100