r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 570

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)
Rev. 1.00 Oct. 01, 2007 Page 504 of 1956
REJ09B0256-0100
Bit
3
2
1
Bit Name
TAI
MAI
RDPEI
Initial
Value
0
0
0
R/W
SH: R/WC
PCI: R
SH: R/WC
PCI: R
SH: R/WC
PCI: R
Description
Target-Abort Interrupt
Indicates that a transaction is terminated with a
target-abort when a device other than the PCIC
functions as a bus master.
0: Target-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Target-abort interrupt occurs
[Set condition]
When a target-abort interrupt occurs.
Master-Abort Interrupt
Indicates that a transaction is terminated with a
master-abort when a device other than the PCIC
functions as a bus master.
0: Master-abort interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Master-abort interrupt occurs
[Set condition]
When a master-abort interrupt occurs.
Read Parity Error Interrupt
The PERR assertion is detected during a data read
when a device other than the PCIC functions as a
bus master.
0: Read parity error interrupt does not occur
[Clear condition]
Write 1 to this bit (write clear).
1: Read parity error interrupt occurs
[Set condition]
When a read parity error interrupt is detected by the
PERR assertion.