r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1371

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

In write data transmission, the contents of the command response and data response should be
analyzed, and then transmission should be triggered. In addition, the data transmission should be
temporarily halted by FIFO full/empty, and it should resume when the preparation has been
completed.
In multiblock transfer, the transfer should be temporarily halted at every block break to select
whether to continue to the next block or to abort the multiblock transfer command by issuing the
CMD12 command or Stop Tran. To continue to the next block, the RD_CONTI and DATAEN
bits should be set to 1. To issue the CMD12 command or Stop Tran, the CMDOFF bit should be
set to 1 to abort the command sequence on the MMCIF side. When using the auto-mode for pre-
defined multiblock transfer, the setting of the RD_CONTI bit or the DATAEN bit between blocks
can be omitted.
Bit
4
3 to 0
Bit Name
DATAEN
—
Initial
Value
0
All 0
R/W
R/W
R
Description
Data Enable
Starts write data transmission by a command with write
data. Resumes write data transmission while the
sequence has been halted by FIFO empty or
termination of block writing in multiblock write.
Write enabled period: (1) after receiving a response to
a command with write data, (2) while sequence is
halted by FIFO empty, (3) when one block writing in
multiblock write is terminated
Write 0: Operation is not affected.
Write 1: Starts or resumes write data transmission.
Reserved
These bits are always read as 0. The write value should
always be 0.
Section 31 Multimedia Card Interface (MMCIF)
Rev. 1.00 Oct. 01, 2007 Page 1305 of 1956
REJ09B0256-0100