r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 371

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

9.5
9.5.1
The sequence of interrupt operations is described below. Figure 9.4 is the flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the INTC.
2. The INTC selects the highest-priority interrupt from the interrupt requests sent, following the
3. The priority level of the interrupt selected by the INTC is compared with the interrupt mask
4. The CPU accepts an interrupt at a break in instructions.
5. The interrupt source code is set in the interrupt event register (INTEVT).
6. SR and program counter (PC) are saved to SSR and SPC, respectively. R15 is saved to SGR at
7. The BL, MD, and RB bits in SR are set to 1.
8. Execution jumps to the start address of the interrupt exception handling routine (the sum of the
In the exception handling routine, execution may branch with the INTEVT value used as its offset
in order to identify the interrupt source. This enables execution to branch to the handling routine
for the individual interrupt source.
Notes: 1. When the INTMU bit in the CPU operating mode register (CPUOPM) is set to 1, the
priority levels set in INTPRI and INT2PRI0 to INT2PRI14. Lower-priority interrupts are held
pending. If two of these interrupts have the same priority level or if multiple interrupts occur
within a single module, the interrupt with the highest priority is selected according to table 9.7.
level (IMASK) set in SR of the CPU. If the priority level is higher than the mask level, the
INTC accepts the interrupt and sends an interrupt request signal to the CPU.
this time.
value set in the vector base register (VBR) and H'0000 0600).
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
3. For some interrupt sources, the interrupt mask setting (INTMSK) for each interrupt
Operation
Interrupt Sequence
interrupt mask level (IMASK) in SR is automatically set to the level of the accepted
interrupt. When the INTMU bit is cleared to 0, the IMASK value in SR is not affected
by the accepted interrupt.
interrupt source that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, wait for the time shown in table 9.8,
and then clear the BL bit or execute an RTE instruction.
source must be cleared by using INTMSKCLR.
Rev. 1.00 Oct. 01, 2007 Page 305 of 1956
Section 9 Interrupt Controller (INTC)
REJ09B0256-0100