r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1248

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(1)
The reset controller controls resetting of the control register, base counter, and trigger generator.
(2)
The control register has the frequency division register and clock select register.
For details, see section 28.3, Register Descriptions.
(3)
The base counter is a 16-bit CLK (external clock BRG input) synchronization counter.
This counter is used to determine timing of a frequency divided clock when it is generated.
(4)
The trigger generator generates rising-edge/falling-edge triggers for a frequency divided clock,
taking timing according to values of the frequency division register and base counter. The triggers
generate the frequency divided clock.
The trigger generator also switches the output between SCIF2_CLK (external clock input) and the
frequency divided clock.
28.6.2
(1)
1. At the first setting of BSGDL2 after a reset, wait time of one bit period or more is required to
2. After the setting stated in 1 above, wait time of one bit period or more is required at the
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REJ09B0256-0100
ensure the clock settling time.
maximum bit rate (BSGDL2 = 65535) before the value of BSGDL2 is changed again.
Reset controller
Control register
Base counter
Trigger generator
Notes on Frequency Division Register Settings
(Example) Period of one bit when BSGDL2 = 2
3.68 (MHz) × 1/2 × 1/16 = 0.115 (MHz) → 8695 (ns)
Restrictions on the BRG