r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1186

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
• Clocked synchronous serial communication mode
• Full-duplex communication capability
• The LSB is transmitted and received first (LSB first).
• On-chip baud rate generator allows any bit rate to be selected.
• Choice of clock source: internal clock from the baud rate generator based on the peripheral
• Four interrupt sources
• The DMA controller (DMAC) can be activated to execute a data transfer by issuing a DMA
• The amount of data in the transmit/receive FIFO registers, and the number of receive errors in
• In asynchronous mode, a timeout error (DR) can be detected during reception.
Rev. 1.00 Oct. 01, 2007 Page 1120 of 1956
REJ09B0256-0100
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other LSIs that have a synchronous communication function.
There is a single serial data communication format.
 Data length: 8 bits
 Receive error detection: Overrun errors
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 16-stage FIFO buffer structure, enabling continuous
serial data transmission and reception.
clock (Pck0) or external clock from the SCIF2_SCK pin
There are four interrupt sources—transmit-FIFO-data-empty, break, receive-FIFO-data-full,
and receive-error—that can issue requests independently.
transfer request in the event of a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
the receive data in the receive FIFO register, can be ascertained.