r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1387

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

31.3.20 Interrupt Status Register 2 (INTSTR2)
INTSTR2 controls the interrupt output of the MMCIF.
FRDYI is set even in the set condition after a clear. To clear FRDYI, disable the flag setting
through FRDYIE in INTCR2.
Note:
Bit
7 to 3
2
1
0
*
Bit Name
—
CDI
FRDY_TU
FRDYI
Cleared by writing 0 after reading 1
Initial value:
Initial
Value
All 0
0
1
0
R/W:
Bit:
—
R
7
0
R/W
R
R/(W)* Card Identification Flag
R
R/(W)* FIFI Ready Completion Flag
—
R
6
0
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
Identifies insert/pullout of card (variation
between high and low of card identification
signal)
[Setting 1 condition]
When insert/pullout of card is identified
while CDIE = 1.
[Clearing 0 condition]
Write 0 after reading CDI = 1.
When the set condition of FRDYI is met
Read value
0: Remaining data in FIFO meets the
1: Remaining data in FIFO does not meet
[Setting 1 condition]
When the DMAEN bit is set while FRDYIE
= 1 and the remaining data in FIFO does
not meet the assert condition specified by
DMACR.
[Clearing 0 condition]
Write 0 after reading FRDYI = 1.
—
R
5
0
assert condition specified by DMACR.
the assert condition specified by
DMACR.
—
R
4
0
—
Section 31 Multimedia Card Interface (MMCIF)
R
3
0
Rev. 1.00 Oct. 01, 2007 Page 1321 of 1956
R/(W)*
CDI
2
0
FRDY_
TU
R
1
1
R/(W)*
FRDYI
0
0
REJ09B0256-0100
Interrupt
output
FRDY
FRDY