r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1558

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 35 USB Host Controller (USBH)
3. Root Hub (Only one port is supported by this LSI.)
• Hub Control
• Port Control
• Clock Generation
• Static SOF Clock
• Data Rate Clock
Rev. 1.00 Oct. 01, 2007 Page 1492 of 1956
REJ09B0256-0100
The Root Hub is a collection of ports which are individually controlled and a hub which
maintains control/status over functions common to all ports. The typical command request
interface to the hub is emulated by the Host Controller Device(HCD) which communicates
directly through the system bus (PCI) to the hub and port controls. The remainder of this
section will divide the discussion into hub and port design responsibilities.
The Root Hub descriptor registers, HcRhDescriptorA and HcRhDescriptorB, are implemented
R/W to allow multiple configuration with minimal changes to the current implementation.
Hub and port indicate the control and the status through the HcRhStatus and HcRhPortStatus
Registers. Each port has its own HcRhPortStatus Registers. A command structure is defined
through these registers which software uses to control the hub and ports. By writing 1 to bit
locations specified in section 35.3, Register Description, the following commands can be
executed. The command functions are discussed in the following sections.
The HC states also reflect the hub state. For example, when the HC is suspended, USB
SUSPEND, the Root Hub is suspended. When the HC is in USB RESUME, the hub generates
the appropriate bus signaling. USB RESET resets the Root Hub. The following sections
describe hub and bus related controls and status.
The Port is responsible for all activities associated with driving and monitoring bus states. The
HCD controls this behavior through the register command interface.
The USB interface is sourced by a 48 MHz clock which allows for a 4x data rate oversampling
to maintain the receiver phase lock. This clock also sources all USB related clock rates (12
MHz).
As the USB system host, the system frame counter is maintained at a constant 1 ms interval.
This requires a static 12 MHz clock. This is created by dividing down the 48 MHz internal
clock source. The clock is enabled when the HC is not in the USB SUSPEND state.
The SIE requires that the transmit and receive clocks operate at 12 Hz. During FS
transmissions, the data rate clock is equivalent to the static 12 MHz SOF clock.
When receiving data, the data rate clock must match that of the source. Working in
conjunction with the phase lock circuitry, the data rate clock is adjusted to maintain a 1 to 1
ratio of data bits and data clocks. This will result in periodic adjustment of the internal 48 MHz
internal clock periods to maintain synchronization with the data source. When the packet is
complete the data rate clock is re-linked to the static 12 MHz clock discussed above.