r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 975

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

23.3.73 Receive Descriptor List Start Address Register (RDLAR)
RDLAR is a 32-bit readable/writable register that specifies the start address of the receive
descriptor list. Descriptors have a boundary configuration in accordance with the descriptor length
indicated by the DL bits in EDMR. This register must not be modified during reception.
Modifications to this register should only be made while reception is disabled by the RR bit (= 0)
in the E-DMAC receive request register (EDRRR).
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name
RDLA[31:0]
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
All 0
R/W
R/W
28
12
0
0
R/W
R/W
27
11
0
0
R/W Description
R/W Receive Descriptor Start Address
R/W
R/W
26
10
0
0
The lower bits are set according to the specified
descriptor length.
16-byte boundary: RDLA[3:0] = 0000
32-byte boundary: RDLA[4:0] = 00000
64-byte boundary: RDLA[5:0] = 000000
R/W
R/W
25
0
9
0
RDLA[31:15]
R/W
R/W
RDLA[15:0]
24
0
8
0
Section 23 Gigabit Ethernet Controller (GETHER)
R/W
R/W
23
0
7
0
R/W
R/W
Rev. 1.00 Oct. 01, 2007 Page 909 of 1956
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0256-0100
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0