r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1596

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 36 USB Function Controller (USBF)

36.3.21 EP3 Data Register (EPDR3)

EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR4 holds one packet of transmit data

for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and

setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after

the data has been transmitted, EP3TS in interrupt flag register 1 is set. This FIFO buffer can be

initialized by means of EP3CLR in the FCLR0 register.

Rev. 1.00 Oct. 01, 2007 Page 1530 of 1956

REJ09B0256-0100

Initial value:

Initial Value R/W Description

Data register for endpoint 3 transfer

These bits are always read as undefined value.

Write value should always be 0.