r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 557

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

(4)
Refer to Section 13.4.4 (1), Accessing This LSI Address Space.
Bit
0
Initial value:
Initial value:
Bit
31 to 20 LAR
19 to 0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Local Address Register 0 (PCILAR0)
Bit:
Bit:
Bit Name

Bit Name
MBARE
R/W
31
15
—
R
R
R
0
0
R/W
30
14
—
R
R
R
0
0
Initial
Value R/W
H'000 SH: R/W
All 0
R/W
Initial
Value
0
29
13
—
R
R
R
0
0
R/W
PCI: R
SH: R
PCI: R
28
12
—
R
R
R
0
0
R/W
SH: R/W
PCI: R
R/W
27
11
—
R
R
R
0
0
Description
Local Address (12 bits)
Specify bits 31 to 20 of the start address in local address
space 0.
The effective bits of LAR depend on the capacity of local
address space 0 as specified in PCILSR0.
The effective bits are as follows:
PCILSR0.LS0([28:20]) = 0 0000 0000: Effective bits are [31:20]
PCILSR0.LS0([28:20]) = 0 0000 0001: Effective bits are [31:21]
PCILSR0.LS0([28:20]) = 0 0000 0011: Effective bits are [31:22]
PCILSR0.LS0([28:20]) = 0 1111 1111: Effective bits are [31:28]
PCILSR0.LS0([28:20]) = 1 1111 1111: Effective bits are [31:29]
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
26
10
—
R
R
R
0
0
LAR
Description
PCI Memory Base Address Register 1 Enable
The local address space 1 can be accessed by setting
this bit to 1.
0: PCIMBAR1 disabled
1: PCIMBAR1 enabled
|
R/W
25
—
R
R
R
0
9
0
R/W
|
24
—
R
R
R
0
8
0
R/W
23
—
R
R
R
0
7
0
Rev. 1.00 Oct. 01, 2007 Page 491 of 1956
R/W
22
—
R
R
R
0
6
0
R/W
21
—
R
R
R
0
5
0
Section 13 PCI Controller (PCIC)
R/W
20
—
R
R
R
0
4
0
19
—
—
R
R
R
R
0
3
0
REJ09B0256-0100
18
—
—
R
R
R
R
0
2
0
17
—
—
R
R
R
R
0
1
0
16
—
—
R
R
R
R
0
0
0