r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 516

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 13 PCI Controller (PCIC)

• Exclusive access (target only)

• Can support cache coherency between a device connected to the PCI bus and system memory

• Supports four external interrupt inputs (INTD to INTA) in host bus bridge mode

• Supports one external interrupt output (INTA) in normal mode

• Supports both big endian and little endian formats for the SuperHyway bus (the PCI bus

• Number of devices which can be connected

The PCIC does not support the following PCI functions.

• Cache support (no SBO or SDONE pin)

• Address wrap-around mechanism

• PCI JTAG (other modules in this LSI can support the JTAG feature)

• Dual address cycles

• Interrupt acknowledge cycles

• Fast back-to-back transfer initiation (supported when performed as a target device)

• Extended ROM for initialization and system boot

Note: When the ratio of the clocks (SHwy clock : PCICLK clock) is in the ranges of (2.1 : 1) to

Rev. 1.00 Oct. 01, 2007 Page 450 of 1956

REJ09B0256-0100

 Once locked, only accessible from the device that accessed the LOCK signal

 The SuperHyway bus in not locked during lock transfer

(PCI target) although device performance may become suboptimal

operates in the little endian format)

 33 MHz: 4 or less

(3.3 : 1), the PCIC cannot be used.