r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 452

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 Local Bus State Controller (LBSC)
11.5.6
When both the MODE4 and MODE3 pins are set to 0 at a power-on reset by the PRESET pin, the
MPX interface is selected for area 0. The MPX interface is selected for areas 1, 2, and 4 to 6 by
the MPX bit in CS1BCR, CS2BCR, and CS4BCR to CS6BCR. The MPX interface provides an
address/data multiplex-type bus protocol and facilitates connection with external memory
controller chips using an address/data multiplex-type 32-bit single bus. A bus cycle consists of an
address phase and a data phase. Address information is output on D25 to D0 and the access size is
output on D31 to D29 in the address phase. The BS signal is asserted for one cycle to indicate the
address phase. The CSn signal is asserted at the rising edge in Tm1 and is negated after the end of
the last data transfer in the data phase. Therefore, a negation cycle does not occur in the case of
minimum pitch access. The FRAME signal is asserted at the rising edge in Tm1 and negated at the
start of the last data transfer cycle in the data phase. Therefore, an external device for the MPX
interface must internally store the address information and access size output in the address phase
and perform data input/output for the data phase. For details, see section 11.5.1, Endian/Access
Size and Data Alignment.
Values output on address pins A25 to A20 are not guaranteed.
In 32-byte transfer, a total of 32 bytes are transferred continuously according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed according to the set bus width. If the access size is larger than the bus
width in this case, a burst access with continuing multiple data cycle occurs after one address
output. The bus is not released during this transfer.
[Legend]
X:
Rev. 1.00 Oct. 01, 2007 Page 386 of 1956
REJ09B0256-0100
D31
0
1
Don't care
MPX Interface
D30
0
1
X
D29
0
1
0
1
X
Access Size
Byte
Word
Longword
Quadword
32-byte burst