r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1141

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Receive Enable

Enables or disables the start of serial reception by the

Serial reception is started when a start bit is detected in

this state in asynchronous mode or a synchronization

clock is input while the RE bit is set to 1.

It should be noted that clearing the RE bit to 0 does not

affect the DR, ER, BRK, RDF, FER, PER, and ORER

flags, which retain their states. Serial reception begins

once the start bit is detected in these states.

0: Reception disabled

1: Reception enabled*

Note: * SCSMR and SCFCR settings must be made,

Receive Error Interrupt Enable

Enables or disables generation of receive-error

interrupt (ERI) and break interrupt (BRI) requests. The

REIE bit setting is valid only when the RIE bit is 0.

Receive-error interrupt (ERI) and break interrupt (BRI)

requests can be cleared by reading 1 from the ER,

BRK, or ORER flag, then clearing the flag to 0, or by

clearing the RIE and REIE bits to 0. When REIE is set

to 1, ERI and BRI interrupt requests will be generated

even if RIE is cleared to 0. In DMAC transfer, this

setting is made if the interrupt controller is to be notified

of ERI and BRI interrupt requests.

0: Receive-error interrupt (ERI) and break interrupt

1: Receive-error interrupt (ERI) and break interrupt

This bit is always read as 0. The write value should

always be 0.

Section 27 Serial Communication Interface with FIFO (SCIF)

(BRI) requests disabled

(BRI) requests enabled

the reception format decided, and the receive

FIFO reset, before the RE bit is set to 1.

Rev. 1.00 Oct. 01, 2007 Page 1075 of 1956

REJ09B0256-0100