r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 820

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 21 Compare Match Timer (CMT)
Note:
21.2.3
CMCNT is a 32-bit register that is used as an up-counter.
A counter operation is set by the compare match timer control/status register (CMCSR).
Therefore, set CMCSR first, before starting a channel operation corresponding to the compare
match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS
bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data
that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are
initialized to H'00000000.
21.2.4
CMCOR is a 32-bit register that sets the compare match period with CMCNT for each channel.
When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this
register become valid. When the register should be written to, write the data that is added H'0000
to the upper half in a 32-bit operation.
An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The
contents of this register are initialized to H'FFFFFFFF.
Rev. 1.00 Oct. 01, 2007 Page 754 of 1956
REJ09B0256-0100
Bit
2 to 0
*
Compare Match Timer Counter (CMCNT)
Compare Match Timer Constant Register (CMCOR)
Bit Name
CKS[2:0] All 0
Only 0 can be written to clear the flag.
Initial
Value
R/W
R/W
Description
Clock Select
These bits select the clock input to CMCNT. When the
STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins
incrementing with the clock selected by these bits.
000: Pck0/8
001: Pck0/32
010: Pck0/128
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited