r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1385

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

31.3.18 DMA Control Register (DMACR)
DMACR sets DMA request signal output. DMAEN enables or disables a DMA request signal.
The DMA request signal is output based on a value that has been set to SET[2:0].
This register should be set before a multiblock transfer command (CMD18 or CMD25) is
executed. Auto mode cannot be used for open-ended multiblock transfers.
Bit
7
6
5 to 3
2 to 0
Bit Name
DMAEN
AUTO

SET[2:0]
Initial value:
Initial
Value
0
0
All 0
000
R/W:
Bit:
DMAEN
R/W
7
0
R/W
R/W
R/W
R
R/W
AUTO
R/W
6
0
Description
0: Disables output of DMA request signal.
1: Enables output of DMA request signal.
Auto Mode for pre-define multiblock transfer using DMA
transfer. For details on auto mode operation, see
section 14, Direct Memory Access Controller (DMAC).
0: Disable auto mode
1: Enable auto mode
Reserved
These bits are always read as 0. The write value should
always be 0.
Sets DMA request signal assert condition.
000: Not output
001: Remaining data in FIFO is 1/4 or less of FIFO capacity.
010: Remaining data in FIFO is 1/2 or less of FIFO capacity.
011: Remaining data in FIFO is 3/4 or less of FIFO capacity.
100: Remaining data in FIFO is 1 byte or more.
101: Remaining data in FIFO is 1/4 or more of FIFO capacity.
110: Remaining data in FIFO is 1/2 or more of FIFO capacity.
111: Remaining data in FIFO is 3/4 or more of FIFO capacity.
—
R
5
0
—
R
4
0
—
Section 31 Multimedia Card Interface (MMCIF)
R
3
0
Rev. 1.00 Oct. 01, 2007 Page 1319 of 1956
R/W
2
0
SET[2:0]
R/W
1
0
R/W
0
0
REJ09B0256-0100