r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 990

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.78 Transmit FIFO Threshold Register (TFTR)
TFTR is a 32-bit readable/writable register that specifies the transmit FIFO threshold at which the
first transmission is started. The actual threshold is 4 times the set value. The E-MAC starts
transmission when the amount of data in the transmit FIFO exceeds the number of bytes specified
by this register, when the transmit FIFO is full, or when one frame of data write is performed. This
register must not be written to during transmission (bits TR[1:0] in EDTRR = 11).
Rev. 1.00 Oct. 01, 2007 Page 924 of 1956
REJ09B0256-0100
Bit
31 to 11
10 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Bit Name

TFT[10:0] All 0
31
15


R
R
0
0
30
14


R
R
0
0
Initial
Value R/W Description
All 0
29
13


R
R
0
0
28
12


R
R
0
0
R
R/W Transmit FIFO Threshold
27
11


R
R
0
0
Reserved
These bits are always read as 0. The write value should
always be 0.
A value in 32-byte units and smaller than the FIFO size
specified by FDR must be set as the transmit FIFO threshold.
H'000: Store and forward modes
H'008: 32 bytes
H'010: 64 bytes
H'018: 128 bytes
H'07F: 508 bytes
H'080: 512 bytes
H'0FF: 1,020 bytes
H'100: 1,024 bytes
H'1FF: 2,044 bytes
H'200: 2,048 bytes
R/W
26
10

R
0
0
:
:
:
R/W
25

R
0
9
0
:
:
:
R/W
24

R
0
8
0
R/W
23

R
0
7
0
R/W
22

R
0
6
0
TFT[10:0]
R/W
21

R
0
5
0
R/W
20

R
0
4
0
R/W
19

R
0
3
0
R/W
18

R
0
2
0
17

R
0
1
0
R/W
16

R
0
0
0