r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1340

Manufacturer Part Number

r5s77631ay266bgv

Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series

Manufacturer

Renesas Electronics Corporation.

Section 30 SIM Card Module (SIM)

2. Confirm that the PER, ORER, and WAIT_ER flags in SCSSR are 0. If one of these flags is set,

3. Repeat steps (2) and (3) in the figure until it can be confirmed that the RDRF flag is set to 1.

4. Read received data from SCRDR.

5. When receiving data continuously, return to step (2).

6. When reception is ended, clear the RE bit to 0.

Interrupt processing can be performed in the above series of processing.

When the RIE bit is set to 1 and the EIO bit is cleared to 0 and if the RDRF flag is set to 1, a

receive data full interrupt (RXI) request is issued. If the RIE bit is set to 1, an error occurs during

reception, and either the ORER, PER, or WAIT_ER flag is set to 1, a transmit/receive error

interrupt (ERI) request is issued.

For details, refer to, Interrupt Operations in section 30.4.5, Data Transmit/Receive Operation.

If a parity error occurs during reception and the PER flag is set to 1, in T = 0 mode the received

data is not transferred to SCRDR, and so this data cannot be read. In T = 1 mode, received data is

transferred to SCRDR, and so this data can be read.

Rev. 1.00 Oct. 01, 2007 Page 1274 of 1956

REJ09B0256-0100

after performing the prescribed receive error processing, clear the PER, ORER, and WAIT_ER