r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1593
r5s77631ay266bgv
Manufacturer Part Number
r5s77631ay266bgv
Description
Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5S77631AY266BGV.pdf
(2026 pages)
- Current page: 1593 of 2026
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36.3.18 EP0s Data Register (EPDR0s)
EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte
command data sent in the setup stage. However, only the command to be processed by a
microprocessor (firmware) is received. The command data to be processed automatically by this
module is not stored.
Since the setup command mast be received, previous data in the buffer is over written with new
data. In other words, when the reception of data in the setup stage starts during read, reception has
priority and read data is invalid.
Note: The EPDR0s register should be read in longword units or eight consecutive times in byte
Bit
31 to 8
7 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit: 31
Bit: 15
units. If reading is stopped before it completes, data received in the subsequent setup stage
is not read successfully.
Bit Name
D[7:0]
—
—
—
—
R
R
30
14
—
—
—
—
R
R
29
13
—
—
—
—
R
R
Initial Value R/W Description
Undefined
Undefined
28
—
12
—
—
—
R
R
27
11
—
—
—
—
R
R
26
—
10
—
—
—
R
R
R
R
25
—
—
—
—
R
R
9
Reserved
These bits are always read as undefined value.
Data register for storing the setup command at the
control-out transfer
24
—
—
—
—
R
R
8
23
—
—
—
R
R
7
Section 36 USB Function Controller (USBF)
Rev. 1.00 Oct. 01, 2007 Page 1527 of 1956
22
—
—
—
R
R
6
21
—
—
—
R
R
5
20
—
—
—
R
R
4
D[7:0]
19
—
—
—
R
R
3
REJ09B0256-0100
18
—
—
—
R
R
2
17
—
—
—
R
R
1
16
—
—
—
R
R
0
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