r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 1224

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Figure 28.6 shows a sample SCIF initialization flowchart.
Rev. 1.00 Oct. 01, 2007 Page 1158 of 1956
REJ09B0256-0100
in SCSCR (leaving TE, RE, TIE,
and BRK in SCFSR and ORER
in SCLSR, then clear them to 0
and MCE in SCFCR, and clear
SCSCR to 1, and set TIE, RIE,
Set RTRG1-0, TTRG1-0 bits,
and RIE bits cleared to 0)
TFCL and RFCL bits to 0
Set CKE1 and CKE0 bits
Set data transfer format
Clear TE and RE bits in
Read flags of ER, DR,
1-bit interval elapsed?
Set TE and RE bits in
Set TFCL and RFCL
Set value in SCBRR
Start of initialization
bits in SCFCR to 1
End of initialization
and REIE bits
SCSCR to 0
in SCSMR
Yes
Figure 28.6 Sample SCIF Initialization Flowchart
Wait
No
[1]
[2]
[3]
[4]
[1]
[2]
[3]
[4]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE, and RE to 0.
Set the data transfer format in SCSMR.
Write a value corresponding to the bit rate into SCBRR.
Wait at least one bit interval, then set the TE bit or RE bit
in SCSCR to 1. Also set the RIE, REIE, and TIE bits.
Setting the TE and RE bits enables the SCIF_TXD and
SCIF_RXD pins to be used. When transmitting, the SCIF
will go to the mark state; when receiving, it will go to the
idle state, waiting for a start bit.
(Not necessary if an external clock is used.)