r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 51

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Figure 31.19 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock
Figure 31.19 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock
Figure 31.20 (1) Example of Operational Flow for Auto-mode Pre-defined Multiblock
Figure 31.20 (2) Example of Operational Flow for Auto-mode Pre-defined Multiblock
Figure 31.21 Operation Flow to Apply the Card Identification Function................................. 1358
Section 32 PC Card Controller (PCC)
Figure 32.1 PC Card Controller Block Diagram....................................................................... 1360
Figure 32.2 Continuous 32-Mbyte Area Mode......................................................................... 1362
Figure 32.3 Continuous 16-Mbyte Area Mode (Area 6)........................................................... 1363
Figure 32.4 SH7763 Interface................................................................................................... 1380
Figure 32.5 PCMCIA Memory Card Interface Basic Timing................................................... 1384
Figure 32.6 PCMCIA Memory Card Interface Wait Timing.................................................... 1385
Figure 32.7 PCMCIA I/O Card Interface Basic Timing ........................................................... 1386
Figure 32.8 PCMCIA I/O Card Interface Wait Timing ............................................................ 1387
Figure 32.9 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................. 1388
Section 33 Audio Codec Interface (HAC)
Figure 33.1 Block Diagram ...................................................................................................... 1392
Figure 33.2 AC97 Frame Slot Structure ................................................................................... 1409
Figure 33.3 Initialization Sequence .......................................................................................... 1412
Figure 33.4 Sample Flowchart for Off-Chip Codec Register Write ......................................... 1413
Figure 33.5 Sample Flowchart for Off-Chip Codec Register Read (1) .................................... 1414
Figure 33.6 Sample Flowchart for Off-Chip Codec Register Read (2) .................................... 1415
Figure 33.7 Sample Flowchart for Off-Chip Codec Register Read (3) .................................... 1416
Section 34 Serial Sound Interface (SSI)
Figure 34.1 Block Diagram of SSI Module .............................................................................. 1420
Figure 34.2 Philips Format (with no Padding).......................................................................... 1439
Figure 34.3 Philips Format (with Padding)............................................................................... 1439
Figure 34.4 Sony Format (with Serial Data First, Followed by Padding Bits) ......................... 1440
Figure 34.5 Matsushita Format (with Padding Bits First, Followed by Serial Data)................ 1440
Figure 34.6 Multichannel Format (2 Channels, No Padding)................................................... 1442
Figure 34.7 Multichannel Format (3 Channels with High Padding)......................................... 1442
Figure 34.8 Multichannel Format (4 Channels, with Padding Bits First, Followed by
Figure 34.9 Basic Sample Format (Transmit Mode with Example System/
Serial Data, with Padding)..................................................................................... 1443
Data Word Length)................................................................................................ 1444
Read Transfer ................................................................................................ 1352
Read Transfer ................................................................................................ 1353
Write Transfer ............................................................................................... 1355
Write Transfer ............................................................................................... 1356
Rev. 1.00 Oct. 01, 2007 Page li of lxvi