r5s77631ay266bgv Renesas Electronics Corporation., r5s77631ay266bgv Datasheet - Page 884

• Manufacturer Part Number: r5s77631ay266bgv
• Description: Renesas 32-bit Risc Microcomputer Superhtm Risc Engine Family Sh-4a Series
• Manufacturer: Renesas Electronics Corporation.

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.6
MAHR is a 32-bit readable/writable register that specifies the upper 32 bits of the 48-bit MAC
address. The settings in this register are normally made in the initialization process after a reset.
The MAC address setting must not be changed while the transmitting and receiving functions are
enabled. Return the E-MAC and E-DMAC to their initial states by means of the SWRT and
SWRR bits in EDMR before making settings again.
Rev. 1.00 Oct. 01, 2007 Page 818 of 1956
REJ09B0256-0100
Bit
31 to 0
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
MAC Address High Register (MAHR)
Bit Name
MA[47:16] All 0
R/W
R/W
31
15
0
0
R/W
R/W
30
14
0
0
R/W
R/W
29
13
0
0
Initial
Value
R/W
R/W
28
12
0
0
R/W
R/W
27
11
R/W
R/W
0
0
R/W
R/W
26
10
0
0
Description
MAC Address Bits 47 to 16
These bits are used to set the upper 32 bits of the MAC
address.
If the MAC address is 01-23-45-67-89-AB
(hexadecimal), set H'01234567 in this register.
R/W
R/W
25
0
9
0
R/W
R/W
24
MA[31:16]
MA[47:32]
0
8
0
R/W
R/W
23
0
7
0
R/W
R/W
22
0
6
0
R/W
R/W
21
0
5
0
R/W
R/W
20
0
4
0
R/W
R/W
19
0
3
0
R/W
R/W
18
0
2
0
R/W
17
0
1
0
R/W
R/W
16
0
0
0