D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 1174

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

TSR0—Timer Status Register 0
Rev.4.00 Sep. 07, 2007 Page 1142 of 1210
REJ09B0245-0400
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
—
—
7
1
—
—
6
1
—
—
5
0
Overflow Flag
0
1
R/(W)*
TCFV
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
4
0
TGR Input Capture/Output Compare Flag D
0
1
R/(W)*
TGFD
TGR Input Capture/Output Compare Flag C
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while TGRD is
3
0
0
1
functioning as input capture register
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare register
• When TCNT value is transferred to TGRC by input capture signal while TGRC
is functioning as input capture register
R/(W)*
TGFC
TGR Input Capture/Output Compare Flag B
2
0
0
1
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as output
• When TCNT value is transferred to TGRB by input capture signal
R/(W)*
TGFB
of MRB in DTC is 0
compare register
while TGRB is functioning as input capture register
1
0
H'FFD5
TGR Input Capture/Output Compare Flag A
0
1
R/(W)*
TGFA
0
0
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When DMAC is activated by TGIA interrupt while
• When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
• When TCNT value is transferred to TGRA
DISEL bit of MRB in DTC is 0
DTA bit of DMABCR in DMAC is 1
as output compare register
by input capture signal while TGRA is functioning
as input capture register
TPU0