D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 226

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

6.10
6.10.1
The chip can release the external bus in response to a bus request from an external device. In the
external bus-released state, the internal bus master continues to operate as long as there is no
external access.
If an internal bus master wants to make an external access in the external bus-released state, or if a
refresh request is generated, it can issue a request off-chip for the bus request to be dropped.
The BREQOPS bit can be used to change the BREQO output pin from PF
6.10.2
In external expanded mode, the bus can be released to an external device by setting the BRLE bit
in BCRL to 1. Driving the BREQ pin low issues an external bus request to the chip. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus-released state.
In the external bus-released state, an internal bus master can perform accesses using the internal
bus. When an internal bus master wants to make an external access, it temporarily defers
activation of the bus cycle, and waits for the bus request from the external bus master to be
dropped. If a refresh request is generated in the external bus-released state, refresh control is
deferred until the external bus master drops the bus request.
If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external
access in the external bus-released state, or when a refresh request is generated, the BREQO pin is
driven low and a request can be made off-chip to drop the bus request.
When the BREQ pin goes high, the BACK pin is driven high at the prescribed timing and the
external bus-released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
If a refresh request and external bus release request occur simultaneously, the order of priority is
as follows:
Rev.4.00 Sep. 07, 2007 Page 194 of 1210
REJ09B0245-0400
(High) External bus release > Internal bus master external access (Low)
(High) Refresh > External bus release (Low)
Bus Release
Overview
Operation
2
to P5
3
.