D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 132

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
5.2
5.2.1
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the
detected edge for NMI.
Only bits 5 to 3, and 1 are described here; for details of the other bits, see section 3, MCU
Operating Modes.
SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two
interrupt control modes for the interrupt controller.
Bit 5
INTM1
0
1
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
Bit 1—IRQ Input Pin Select (IRQPAS): Selects switching of the pins that can be used for input
of IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports.
Rev.4.00 Sep. 07, 2007 Page 100 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Register Descriptions
System Control Register (SYSCR)
Bit 4
INTM0
1
1
0
0
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
:
:
R/W
Interrupt
Control Mode
0
2
7
0
6
0
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
INTM1
R/W
5
0
INTM0
R/W
4
0
NMIEG
R/W
0
3
LWROD IRQPAS
R/W
2
0
R/W
1
0
(Initial value)
(Initial value)
RAME
R/W
0
1

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