D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 275
![MCU 3V 0K 144-QFP](/photos/28/61/286127/144-bfqfp_sml.jpg)
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 275 of 1246
- Download datasheet (7Mb)
Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external
requests, SCI transmit-data-empty/receive-data-full interrupts, and TPU channel 0 to 5 compare
match/input capture A interrupts. External requests can be set for channel B only.
Figure 7.4 shows an example of the setting procedure for sequential mode.
Sequential mode setting
and transfer destination
Set number of transfers
Set transfer source
Read DMABCRL
Set DMABCRH
Sequential mode
Set DMABCRL
Set DMACR
addresses
Figure 7.4 Example of Sequential Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address and transfer
[3] Set the number of transfers in ETCR.
[4] Set each bit in DMACR.
[5] Read the DTE bit in DMABCRL as 0.
[6] Set each bit in DMABCRL.
• Specify enabling or disabling of transfer end
• Set the DTE bit to 1 to enable transfer.
• Clear the FAE bit to 0 to select short address
• Specify enabling or disabling of internal
destination address in MAR and IOAR.
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the RPE bit to 0 to select sequential
• Specify the transfer direction with the DTDIR
• Select the activation source with bits DTF3 to
mode.
interrupt clearing with the DTA bit.
decremented with the DTID bit.
mode.
bit.
DTF0.
interrupts with the DTIE bit.
Rev.4.00 Sep. 07, 2007 Page 243 of 1210
REJ09B0245-0400
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