D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 767

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
19.2.2
Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the
EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L
(BCRL).
Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF *
to be internal addresses or external addresses.
Notes: 1. Do not access a reserved area.
19.3
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD2 to MD0) and the EAE
bit in BCRL. These settings are shown in tables 19.2 and 19.3.
Bit 5
Bit
Initial value :
R/W
0
1
2. Addresses H'010000 to H'05FFFF in the H8S/2339.
On-chip ROM
Addresses H'010000 to H'03FFFF *
or reserved area *
Bus Control Register L (BCRL)
Operation
H8S/2339, H8S/2338
:
:
BRLE
R/W
7
0
1
BREQOE
in single-chip mode
R/W
6
0
EAE
R/W
Addresses H'010000 to H'01FFFF are on-chip ROM or
address H'020000 to H'03FFFF are reserved area *
5
1
2
are external addresses in external expanded mode
Description
R/W
1
4
Rev.4.00 Sep. 07, 2007 Page 735 of 1210
DDS
R/W
3
1
H8S/2337
R/W
2
1
REJ09B0245-0400
WDBE
R/W
(Initial value)
1
0
WAITE
1
R/W
0
0
2
are

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