D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 728

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by
the SCI in receive mode and transmit mode as described below.
• Retransfer operation when SCI is in receive mode
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
Rev.4.00 Sep. 07, 2007 Page 696 of 1210
REJ09B0245-0400
Figure 15.11 illustrates the retransfer operation when the SCI is in receive mode.
automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is
automatically cleared to 0.
error signal transmission.
RDRF
PER
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 15.11 Retransfer Operation in SCI Receive Mode
nth transfer frame
[2]
[1]
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Retransferred frame
(DE)
[4]
[3]
Ds D0 D1 D2 D3 D4
Transfer
frame n+1