D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 221

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH
is set to 1, an idle cycle is inserted at the start of the write cycle.
Figure 6.32 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
φ
(a) Idle cycle not inserted
T
1
Bus cycle A
(ICIS0 = 0)
T
2
Figure 6.32 Example of Idle Cycle Operation (2)
T
3
Long output
floating time
Bus cycle B
T
1
T
2
Data
collision
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
φ
Rev.4.00 Sep. 07, 2007 Page 189 of 1210
T
1
Bus cycle A
(b) Idle cycle inserted
T
2
(ICIS0 = 1 (initial value))
T
3
REJ09B0245-0400
T
I
Bus cycle B
T
1
T
2