D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 321

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

7.7
DMAC Register Access during Operation: Except for forced termination, the operating
(including transfer waiting state) channel setting should not be changed. The operating channel
setting should only be changed when transfer is disabled.
Also, MAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
(a) DMAC control starts one cycle before the bus cycle, with output of the internal address.
DMA Internal
address
DMA register
operation
DMA control
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.40 shows an example of the update timing for DMAC registers in dual address
transfer mode.
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2'] Transfer destination address register MAR operation (incremented/decremented/fixed)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Notes: 1. In single address transfer mode, the update timing is the same as [1].
φ
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Block transfer counter ETCR operation (decremented, in last transfer cycle of a block
in block transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
Usage Notes
2. The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Idle
[1]
Transfer
source
Read
Figure 7.40 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
Rev.4.00 Sep. 07, 2007 Page 289 of 1210
[1]
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Transfer
Write
DMA write
[3]
REJ09B0245-0400
Dead
DMA
dead
Idle