D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 390

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Port 3 Register (PORT3)
Note: * Determined by state of pins P3
PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3
pins (P3
Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified.
If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3
read is performed while P3DDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORT3 contents are determined by the pin states, as
P3DDR and P3DR are initialized. PORT3 retains its prior state in software standby mode.
Port 3 Open Drain Control Register (P3ODR)
P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3
pin (P3
Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified.
Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin,
while clearing the bit to 0 makes the pin a CMOS output pin.
P3ODR is initialized to H'00 (bits 5 to 0) by a reset, and in hardware standby mode. It retains its
prior state in software standby mode.
Rev.4.00 Sep. 07, 2007 Page 358 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
5
5
to P3
to P3
0
:
:
:
:
).
0
) must always be performed on P3DR.
Undefined Undefined
Undefined Undefined
—
—
—
—
7
7
—
—
—
—
6
6
P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
5
to P3
R/W
P35
— *
R
5
5
0
0
.
R/W
P34
— *
R
4
4
0
R/W
P33
— *
R
3
3
0
R/W
P32
— *
R
2
2
0
R/W
P31
— *
R
1
1
0
R/W
P30
— *
R
0
0
0