D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 422

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the
LWR pin, switches the IRQ
initialized to H'01 by a reset, and in hardware standby mode. It is not initialized in software
standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select either of
two interrupt control modes for the interrupt controller. For details, see section 5, Interrupt
Controller.
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. For details, see
section 5, Interrupt Controller.
Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. For details, see
section 9.16, Port F.
Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins IRQ
IRQ
Bit 1
IRQPAS
0
1
Bit 0—RAM Enable (RAME): Enables or disables on-chip RAM. For details, see section 18,
RAM.
Rev.4.00 Sep. 07, 2007 Page 390 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
4
to IRQ
7
input is always performed from one of the ports.
:
:
Description
P9
P5
4
0
R/W
to P9
to P5
7
0
7
3
used for IRQ
used for IRQ
4
to IRQ
6
0
7
input pins, and selects the detected edge for NMI. SYSCR is
4
4
INTM1
R/W
to IRQ
to IRQ
5
0
7
7
input
input
INTM0
R/W
4
0
NMIEG
R/W
0
3
LWROD IRQPAS
R/W
2
0
R/W
1
0
4
(Initial value)
to IRQ
RAME
R/W
7
0
1
.

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