D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 683
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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[3]
No
No
Read receive data in RDR, and
Clear ORER flag in SSR to 0
clear RDRF flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
Overrun error handling
All data received?
Start of reception
Error handling
Figure 14.18 Sample Serial Reception Flowchart
Initialization
ORER = 1?
RDRF = 1?
<End>
<End>
Yes
Yes
No
(Continued below)
Error processing
Yes
[2]
[1]
[3]
[4]
[5]
Rev.4.00 Sep. 07, 2007 Page 651 of 1210
[1]
[2] [3]
[4]
[5]
The RxD pin is automatically
designated as the receive data
input pin.
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DMAC or
DTC is activated by a
receive-data-full interrupt (RXI)
request and the RDR value is
read.
SCI initialization:
Receive error handling:
REJ09B0245-0400
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