D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 509

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.2.9
TSYR is an 8-bit readable/writable register that selects independent operation or synchronous
operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when
the corresponding bit in TSYR is set to 1.
TSYR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: Must always be written with 0.
Bits 5 to 0—Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is
independent of or synchronized with other channels.
When synchronous operation is selected, synchronous presetting of multiple channels *
synchronous clearing through counter clearing on another channel *
Bit n
SYNCn
0
1
Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1.
Bit
Initial value :
R/W
2. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source
Timer Synchro Register (TSYR)
must also be set by means of bits CCLR2 to CCLR0 in TCR.
Description
other channels)
TCNT synchronous presetting *
TCNTn operates independently (TCNT presetting/clearing is unrelated to
TCNTn performs synchronous operation
:
:
7
0
6
0
SYNC5
R/W
5
0
1
/synchronous clearing *
SYNC4
R/W
0
4
Rev.4.00 Sep. 07, 2007 Page 477 of 1210
SYNC3
R/W
3
0
2
2
are possible.
is possible
SYNC2
R/W
2
0
SYNC1
REJ09B0245-0400
R/W
1
0
(Initial value)
1
, and
n = 5 to 0
SYNC0
R/W
0
0

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