D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 147

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for
the selected interrupts in interrupt acceptance control according to the interrupt priority level
(IPR).
The interrupt source selected is the interrupt with the highest priority level, and whose priority
level set in IPR is higher than the mask level.
Table 5.7
Interrupt Control Mode
0
2
Default Priority Determination: When an interrupt is selected by 8-level control, its priority is
determined and a vector number is generated.
If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the
interrupt source with the highest priority according to the preset default priorities is selected and
has a vector number generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.8 shows operations and control signal functions in each interrupt control mode.
Table 5.8
Legend:
X:
IM: Used as interrupt mask bit
PR: Sets priority
—:
Notes: 1. Set to 1 when interrupt is accepted.
Interrupt
Control
: Interrupt operation control performed
Mode
0
2
No operation (All interrupts enabled)
Not used
2. Keep the initial setting.
INTM1 INTM0
Interrupts Selected in Each Interrupt Control Mode (2)
Operations and Control Signal Functions in Each Interrupt Control Mode
0
1
Setting
0
0
X
Selected Interrupts
All interrupts
Highest-priority-level (IPR) interrupt whose priority level is greater
than the mask level (IPR > I2 to I0)
Acceptance
Interrupt
Control
— *
IM
I
1
X
8-Level Control
I2 to I0
IM
—
Rev.4.00 Sep. 07, 2007 Page 115 of 1210
— *
IPR
PR
2
Default Priority
Determination
REJ09B0245-0400
T (Trace)
—
T