D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 793

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

• Before branching to the programming control program (RAM area H'FF8400 to H'FFFBFF),
• Boot mode can be entered by making the pin settings shown in table 19.9 and executing a
• If the mode pin input levels are changed (for example, from low to high) during a reset, the
Notes: 1. Mode pins input must satisfy the mode programming setup time (t
19.6.2
When set to user program mode, the chip can program and erase its flash memory by executing a
user program/erase control program. Therefore, on-board reprogramming of the on-chip flash
memory can be carried out by providing on-board means supply of programming data, and storing
a program/erase control program in part of the program area if necessary.
To select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7).
In this mode, on-chip supporting modules other than flash memory operate as they normally
would in modes 6 and 7.
The flash memory itself cannot be read while the SWE bit is set to 1 to perform programming or
erasing, so the control program that performs programming and erasing should be run in on-chip
The contents of the CPU’s internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control program.
In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area
must be specified for use by the programming control program.
Initial settings must also be made for the other on-chip registers.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
the mode pins, and executing reset release *
overflow reset.
Do not change the mode pin input levels in boot mode.
state of ports with multiplexed address functions and bus control output pins (AS, RD, HWR)
will change according to the change in the microcomputer’s operating mode *
Therefore, care must be taken to make pin settings to prevent these pins from becoming output
signal pins during a reset, or to prevent collision with signals outside the microcomputer.
the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
reset-start.
2. See section 9, I/O Ports.
User Program Mode
respect to the reset release timing.
1
. Boot mode can also be cleared by a WDT
Rev.4.00 Sep. 07, 2007 Page 761 of 1210
MDS
REJ09B0245-0400
2
= 200 ns) with
.