D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 22

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

10.5 Interrupts ........................................................................................................................... 508
10.6 Operation Timing.............................................................................................................. 511
10.7 Usage Notes ...................................................................................................................... 519
Section 11 Programmable Pulse Generator (PPG)
11.1 Overview........................................................................................................................... 529
11.2 Register Descriptions ........................................................................................................ 533
11.3 Operation........................................................................................................................... 543
11.4 Usage Notes ...................................................................................................................... 552
Rev.4.00 Sep. 07, 2007 Page xx of xxx
10.4.3 Synchronous Operation........................................................................................ 488
10.4.4 Buffer Operation .................................................................................................. 490
10.4.5 Cascaded Operation ............................................................................................. 494
10.4.6 PWM Modes ........................................................................................................ 496
10.4.7 Phase Counting Mode .......................................................................................... 502
10.5.1 Interrupt Sources and Priorities............................................................................ 508
10.5.2 DTC/DMAC Activation....................................................................................... 510
10.5.3 A/D Converter Activation.................................................................................... 510
10.6.1 Input/Output Timing ............................................................................................ 511
10.6.2 Interrupt Signal Timing........................................................................................ 515
11.1.1 Features................................................................................................................ 529
11.1.2 Block Diagram..................................................................................................... 530
11.1.3 Pin Configuration................................................................................................. 531
11.1.4 Registers............................................................................................................... 532
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL)................................... 533
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 534
11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 535
11.2.4 Notes on NDR Access ......................................................................................... 535
11.2.5 PPG Output Control Register (PCR).................................................................... 537
11.2.6 PPG Output Mode Register (PMR) ..................................................................... 539
11.2.7 Port 1 Data Direction Register (P1DDR)............................................................. 541
11.2.8 Port 2 Data Direction Register (P2DDR)............................................................. 542
11.2.9 Module Stop Control Register (MSTPCR) .......................................................... 542
11.3.1 Overview.............................................................................................................. 543
11.3.2 Output Timing...................................................................................................... 544
11.3.3 Normal Pulse Output............................................................................................ 545
11.3.4 Non-Overlapping Pulse Output............................................................................ 547
11.3.5 Inverted Pulse Output .......................................................................................... 550
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 551
11.4.1 Operation of Pulse Output Pins............................................................................ 552
11.4.2 Note on Non-Overlapping Output........................................................................ 552
.................................................... 529