D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 428

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Port A Open Drain Control Register (PAODR)
PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each
port A pin (PA
PAODR is valid only in mode 7. Do not PAODR bits to 1 in modes 4 to 6.
Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while
clearing the bit to 0 makes the pin a CMOS output.
PAODR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port Function Control Register 1 (PFCR1)
PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to
H'0F by a reset, and in hardware standby mode.
Bits 7 to 4—Reserved: Only 0 should be written to these bits.
Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A
in modes 4 to 6.
Bit 3
A23E
0
1
Rev.4.00 Sep. 07, 2007 Page 396 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
7
Description
DR is output when PA7DDR = 1
A
to PA
23
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
is output when PA7DDR = 1
R/W
R/W
7
0
7
0
0
).
R/W
R/W
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
A23E
R/W
R/W
0
1
3
3
A22E
R/W
R/W
2
0
2
1
23
). This bit is valid
A21E
R/W
R/W
1
0
1
1
(Initial value)
A20E
R/W
R/W
0
0
0
1

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