D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 286

MCU 3V 0K 144-QFP

D12332VFC25

Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet

Specifications of D12332VFC25

Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.5.6
In normal mode, transfer is performed with channels A and B used in combination. Normal mode
can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA
to 0.
In normal mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCRA. The transfer source is
specified by MARA, and the transfer destination by MARB.
Table 7.10 summarizes register functions in normal mode.
Table 7.10 Register Functions in Normal Mode
Register
23
23
Legend:
MARA: Memory address register A
MARB: Memory address register B
ETCRA: Execute transfer count register A
MARA and MARB specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or
word is transferred, or can be fixed.
Incrementing, decrementing, or holding a fixed value can be set separately for MARA and
MARB.
The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a
transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends.
If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536.
Rev.4.00 Sep. 07, 2007 Page 254 of 1210
REJ09B0245-0400
15
Normal Mode
MARA
MARB
ETCRA
0
0
0
Function
Source address
register
Destination
address register
Transfer counter Number of transfers Decremented every
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
transfer; transfer ends
when count reaches
H'0000

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