D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 574
![MCU 3V 0K 144-QFP](/photos/28/61/286127/144-bfqfp_sml.jpg)
D12332VFC25
Manufacturer Part Number
D12332VFC25
Description
MCU 3V 0K 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.DF2338VFC25V.pdf
(1246 pages)
Specifications of D12332VFC25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412332VFC25
HD6412332VFC25
HD6412332VFC25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12332VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 574 of 1246
- Download datasheet (7Mb)
11.2.8
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2.
Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must
be set to 1. For further information about P2DDR, see section 9, I/O Port.
11.2.9
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and
a transition is made to module stop mode. Registers cannot be read or written to in module stop
mode. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 11—Module Stop (MSTP11): Specifies the PPG module stop mode.
Bit 11
MSTP11
0
1
Rev.4.00 Sep. 07, 2007 Page 542 of 1210
REJ09B0245-0400
Bit
Initial value :
R/W
Bit
Initial value :
R/W
Port 2 Data Direction Register (P2DDR)
Module Stop Control Register (MSTPCR)
Description
PPG module stop mode cleared
PPG module stop mode set
:
:
:
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
15
0
W
7
0
14
0
13
1
W
6
0
MSTPCRH
12
1
11
1
W
5
0
10
1
1
9
W
4
0
8
1
7
1
W
0
3
6
1
5
1
W
2
0
MSTPCRL
4
1
3
1
W
1
0
2
1
(Initial value)
1
1
W
0
0
0
1
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