D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 164

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

6.1.3
Table 6.1 summarizes the pins of the bus controller.
Table 6.1
Rev.4.00 Sep. 07, 2007 Page 132 of 1210
REJ09B0245-0400
Name
Address strobe
Read
High write/write enable
Low write
Chip select 0
Chip select 1
Chip select 2/row
address strobe 2
Chip select 3/row
address strobe 3
Chip select 4/row
address strobe 4
Chip select 5/row
address strobe 5
Chip select 6
Chip select 7
Upper column address
strobe
Lower column address
strobe
Pin Configuration
Bus Controller Pins
Symbol
AS
RD
HWR
LWR
CS
CS
CS
CS
CS
CS
CS
CS
CAS
LCAS
0
1
2
3
4
5
6
7
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Strobe signal indicating that address output on
address bus is enabled.
Strobe signal indicating that external space is
being read.
Strobe signal indicating that external space is to
be written, and upper half (D
is enabled.
2-CAS DRAM write enable signal.
Strobe signal indicating that external space is to
be written, and lower half (D
is enabled.
Strobe signal indicating that area 0 is selected.
Strobe signal indicating that area 1 is selected.
Strobe signal indicating that area 2 is selected.
DRAM row address strobe signal when area 2 is
in DRAM space.
Strobe signal indicating that area 3 is selected.
DRAM row address strobe signal when area 3 is
in DRAM space.
Strobe signal indicating that area 4 is selected.
DRAM row address strobe signal when area 4 is
in DRAM space.
Strobe signal indicating that area 5 is selected.
DRAM row address strobe signal when area 5 is
in DRAM space.
Strobe signal indicating that area 6 is selected.
Strobe signal indicating that area 7 is selected.
2-CAS DRAM upper column address strobe
signal.
DRAM lower column address strobe signal.
Function
7
15
to D
to D
0
) of data bus
8
) of data bus