D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 791

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2339 F-ZTAT chip
measures the low period of the asynchronous SCI communication data (H'00) transmitted
continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1
stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the
measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate
adjustment. The host should confirm that this adjustment end indication (H'00) has been received
normally, and transmit one H'55 byte to the chip. If reception cannot be performed normally,
initiate boot mode again (reset), and repeat the above operations. Depending on the host’s
transmission bit rate and the chip’s system clock frequency, there will be a discrepancy between
the bit rates of the host and the chip. To ensure correct SCI operation, the host’s transfer bit rate
should be set to 9,600 or 19,200 bps.
Table 19.10 shows typical host transfer bit rates and system clock frequencies for which automatic
adjustment of the MCU’s bit rate is possible. The boot program should be executed within this
system clock range.
Table 19.10 System Clock Frequencies for which Automatic Adjustment of H8S/2339
Host Bit Rate
19,200 bps
9,600 bps
On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FF7C00 to
H'FF83FF is reserved for use by the boot program, as shown in figure 19.12. The area to which the
programming control program is transferred is H'FF8400 to H'FFFBFF. The boot program area
can be used when the programming control program transferred into RAM enters the execution
state. A stack area should be set up as required.
F-ZTAT Bit Rate is Possible
Start
bit
Figure 19.11 Automatic SCI Bit Rate Adjustment
D0
System Clock Frequency for which Automatic Adjustment
of H8S/2339 F-ZTAT Bit Rate is Possible
16 MHz to 25 MHz
8 MHz to 25 MHz
Low period (9 bits) measured (H'00 data)
D1
D2
D3
D4
Rev.4.00 Sep. 07, 2007 Page 759 of 1210
D5
D6
D7
(1 or more bits)
REJ09B0245-0400
High period
Stop
bit