D12332VFC25 Renesas Electronics America, D12332VFC25 Datasheet - Page 273

• Manufacturer Part Number: D12332VFC25
• Description: MCU 3V 0K 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12332VFC25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 106
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412332VFC25; HD6412332VFC25

• External request
Block Transfer Mode: In response to a single transfer request, a block transfer of the specified
block size is carried out. This is repeated the specified number of times, once each time there is a
transfer request. At the end of each single block transfer, one address is restored to its original
setting. An interrupt request can be sent to the CPU or DTC when the specified number of block
transfers have been completed. Both addresses are specified as 24 bits.
7.5.2
Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode,
MAR is updated after each byte or word transfer in response to a single transfer request, and this is
executed the number of times specified in ETCR.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.6 summarizes register functions in sequential mode.
Table 7.6
Register
23
23
Legend:
MAR:
IOAR:
ETCR: Execute transfer count register
DTDIR: Data transfer direction bit
In response to a single transfer request, the specified number of transfers are carried out, one
byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the
specified number of transfers have been completed. Both addresses are specified as 24 bits.
H'FF
Memory address register
I/O address register
15
15
Sequential Mode
MAR
Register Functions in Sequential Mode
ETCR
IOAR
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Rev.4.00 Sep. 07, 2007 Page 241 of 1210
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Operation
Incremented/
decremented every
transfer
Fixed
transfer; transfer
ends when count
reaches H'0000
REJ09B0245-0400