HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 1031

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3.4
Only longword (32-bit) access of the PCIC's internal local registers and configuration registers
from the CPU is supported.
(It is possible to use PIO transfers to perform byte, word, and longword access of the memory
space and I/O space on the PCI bus.)
If an attempt is made to access these registers using other than the prescribed access size, zero is
returned when reading and writing is ignored. The same is true if you attempt to access the
reserved areas in the register area in the PCIC.
Some of the configuration registers and local registers can be accessed both from the CPU and
from the PCI device(s). Therefore, arbitration is performed for both types of access and either the
CPU or PCI device access made to wait according to the access timing.
In the read bus cycle from the CPU, the internal bus cycle for the peripheral module is made to
wait until the data is actually ready. In the write bus cycle, the bus cycle of the internal bus for
peripheral modules ends with the data having been written to the interface (register located
immediately after the PCIC input) register on the internal bus for peripheral modules, but the data
is not actually written to the local register(s) or PCI bus until the following clock cycle. If it is
necessary to check that the data has actually been written, read the register to which the data was
to have been written. This is because the read cycle must be after the write cycle has completed.
When accessing from a PCI device, the PCI bus cycle is caused to wait until the read or write
operation has actually completed.
The internal bus for peripheral modules used for read/write operations from the CPU operates only
with big endians.
22.3.5
The PCIC has the following PCI bus host functions (host devices):
• Inter-PCI device arbitration function
• Configuration register access function
• Special cycle generation function
• Reset output function
• Clock output function
Local Register Access
Host Functions
Rev.4.00 Oct. 10, 2008 Page 931 of 1122
22. PCI Controller (PCIC)
REJ09B0370-0400