HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 84

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 14.50 Single Address Mode/Burst Mode/External Device → External Bus Data
Figure 14.51 Single Address Mode/Burst Mode/External Bus → External Device Data
Figure 14.52 Single Address Mode/Burst Mode/External Device → External Bus Data
Figure 14.53 Block Diagram of the DMAC ................................................................................ 583
Figure 14.54 DTR Format (Transfer Request Format) (SH7751R)............................................. 594
Figure 14.55 Single Address Mode/Burst Mode/External Bus → External Device 32-Byte
Figure 14.56 Single Address Mode/Cycle Steal Mode/External Bus → External Device/
Section 15 Serial Communication Interface (SCI)
Figure 15.1 Block Diagram of SCI............................................................................................ 605
Figure 15.2 SCK Pin.................................................................................................................. 621
Figure 15.3 TxD Pin .................................................................................................................. 622
Figure 15.4 RxD Pin.................................................................................................................. 622
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Figure 15.6 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 636
Figure 15.7 Sample SCI Initialization Flowchart ...................................................................... 637
Figure 15.8 Sample Serial Transmission Flowchart .................................................................. 638
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
Figure 15.10 Sample Serial Reception Flowchart (1).................................................................. 641
Figure 15.11 Example of SCI Receive Operation (Example with 8-Bit Data, Parity,
Figure 15.12 Example of Inter-Processor Communication Using Multiprocessor Format
Figure 15.13 Sample Multiprocessor Serial Transmission Flowchart ......................................... 647
Figure 15.14 Example of SCI Transmit Operation (Example with 8-Bit Data,
Figure 15.15 Sample Flowchart of Multiprocessor Serial Reception with Interrupt Generation 651
Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 652
Figure 15.16 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 653
Figure 15.17 Example of SCI Receive Operation (Example with 8-Bit Data,
Figure 15.18 Data Format in Synchronous Communication ....................................................... 655
Figure 15.19 Sample SCI Initialization Flowchart ...................................................................... 657
Rev.4.00 Oct. 10, 2008 Page lxxxii of xcviii
REJ09B0370-0400
Transfer/Direct Data Transfer Request to Channel 2 ............................................. 577
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ 578
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2........ 579
Block Transfer/Channel 0 On-Demand Data Transfer........................................... 598
32-Byte Block Transfer/On-Demand Data Transfer on Channel 4 ........................ 599
Parity, Two Stop Bits)............................................................................................ 634
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 640
One Stop Bit).......................................................................................................... 644
(Transmission of Data H'AA to Receiving Station A) ........................................... 645
Multiprocessor Bit, One Stop Bit).......................................................................... 649
Multiprocessor Bit, One Stop Bit).......................................................................... 654