HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 17

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Item
5.6.1 Resets
(3) H-UDI Reset
(4) Instruction TLB
Multiple-Hit Exception
(5) Data TLB Multiple-
Hit Exception
5.6.2 General
Exceptions
(11) General FPU
Disable Exception
Page
149
150
151
162
Revision (See Manual for Details)
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Description amended
In the initialization processing, the VBR register is set to H'0000
0000, and in SR, the MD, RB, and BL bits are set to 1, the FD
bit is cleared to 0, and the interrupt mask bits (IMASK) are set
to B'1111.
…
SR.IMASK = B'1111;
Note amended
Note:
*
FPU instructions are instructions in which the first 4
bits of the instruction code are H'F (but excluding
undefined instruction H'FFFD), and the LDS, STS,
LDS.L, and STS.L instructions corresponding to
FPUL and FPSCR.
Rev.4.00 Oct. 10, 2008 Page xv of xcviii
REJ09B0370-0400