HD6417751RF240V Renesas Electronics America, HD6417751RF240V Datasheet - Page 958

• Manufacturer Part Number: HD6417751RF240V
• Description: MPU 1.5/3.3V 0K PB-FREE 256-QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417751RF240V

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 240MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 39
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-QFP Exposed Pad, 256-eQFP, 256-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22. PCI Controller (PCIC)
PCI configuration register 1 (PCICONF1) is a 32-bit read/partial-write register that includes the
status and command PCI configuration registers stipulated in the PCI local bus specifications. The
status is read from bits 31 to 16 (status register) in the event of an error on the PCI bus. Bits 15 to
0 (command register) contain the settings required for initiating transfers on the PCI bus.
Bits 31 to 27, 24, 8 to 6, and 2 to 0 can be written to from both the PP and PCI buses. However,
bits 31 to 27 and 24 are write-clear bits that are cleared when 1 is written to them. Bits 22 and 21
can be written to from the PP bus. Other bits are fixed in hardware.
The PCICONF1 register is initialized to H'02900080 at a power-on reset or software reset.
Always write to this register before initiating transfers on the PCI bus.
Bit 31—Parity Error Detection Status (DPE): Indicates the detection of a parity error in read
data when the PCIC is operating as the master, or a party error in write data when the PCIC is
operating as a target.
Bit 31: DPE
0
1
Bit 30—System Error Output Status (SSE): Indicates the SERR assert operation of the PCIC.
Bit 30: SSE
0
1
Bit 29—Master abort receive status (RMA): Indicates the termination of transaction by master
abort when the PCIC is operating as the master.
Bit 29: RMA
0
1
Rev.4.00 Oct. 10, 2008 Page 858 of 1122
REJ09B0370-0400
Description
No parity error detected by device
Parity error detected by device
Set this bit regardless of the parity error response bit (bit 6) on the device
Description
Device not asserting SERR
Device asserting SERR (Value retained until cleared)
Description
No transaction termination using bus master abort
Detection by bus master of transaction termination by bus master abort
However, in the case of a master abort in a special cycle, notify the master
devices that are not set
(Initial value)
(Initial value)
(Initial value)